This invention relates to digital signal phase mixers. More particularly, this invention relates to digital phase mixers with enhanced speed.
A phase mixer typically receives two input signals and outputs a signal having a phase between the phases of the two input signals. Select signals can be used to determine the phase of the output signal. The number of bits in the select signals can indicate the number of possible intermediate phases, equally-spaced apart, that can be generated by the phase mixer. For example, two signals having a respective phase of 45° and 90° can be input to a phase mixer, which can then output a signal having a phase between 45° and 90°. If the select signals each have nine bits, the phase mixer can generate an output signal having one of eight possible intermediate phases (e.g., 50°, 55°, 60°, 65°, 70°, 75°, 80°, and 85°).
One voltage source typically drives the input signals, the select signals, and the output signal. Generation of the output signal typically results in a propagation delay, which increases the desired phase of the output signal. This non-zero propagation delay can impede the high speed performance of a phase mixer.
In view of the foregoing, it would be desirable to provide digital phase mixers with reduced propagation delay.